1. Field
Example embodiments relate to an interposer chip, a multi-chip package including the interposer chip, and a method of manufacturing the interposer chip and the multi-chip package. More particularly, example embodiments relate to an interposer chip configured to electrically connect two semiconductor chips having different sizes from each other, a multi-chip package including the interposer chip, and a method of manufacturing the interposer chip.
2. Description of the Related Art
Generally, a plurality of semiconductor fabrication processes may be performed on a semiconductor substrate to form a plurality of semiconductor chips. In order to mount the semiconductor chips on a printed circuit board (PCB), a packaging process may be performed on the semiconductor chips to form semiconductor packages.
In order to increase a storage capacity of the semiconductor package, a stacked package including sequentially stacked semiconductor packages may be used. The stacked semiconductor chips, or chips stacked on package substrate may be electrically connected with each other via conductive wires.
However, when the semiconductor chips and/or a package substrate have different sizes, it may be difficult to directly connect the stacked semiconductor chips with each other or with the package substrate using the conductive wires due to a length limit of the conductive wire. In order to electrically connect the semiconductor chips having different sizes, an interposer chip may be interposed between the semiconductor chips or between one or more semiconductor chips and a package substrate. The semiconductor chips may be indirectly connected with each other or with the package substrate via the interposer chip.
The interposer chip may include a substrate, and conductive patterns built in the substrate. The conductive patterns may be electrically connected to the semiconductor chips and/or the package substrate.
The conductive patterns may be electrically isolated from each other. Therefore, the electrically isolated conductive patterns may not be tested until the interposer chip is connected to stacked semiconductor chips. That is, in current testing methods, in order to test electrical characteristics of the conductive patterns, the conductive patterns are first connected to the semiconductor chips. Thus, when the conductive patterns are determined to be defective, the working semiconductor chips as well as the defective interposer chip may be scrapped.